[CITASA] Int. J. Embedded and Real-Time Communication Systems (IJERTCS): Contents of the latest issue and Call for papers

Seppo Virtanen seppo.virtanen at utu.fi
Thu Jun 20 04:21:33 EDT 2013


The contents of the latest issue of:

International Journal of Embedded and Real-Time Communication Systems 
(IJERTCS)
Official Publication of the Information Resources Management Association
Volume 4, Issue 1, January – March 2013
Published: Quarterly in Print and Electronically
ISSN: 1947-3176 EISSN: 1947-3184
Published by IGI Publishing, Hershey-New York, USA
www.igi-global.com/ijertcs

Editor-in-Chief: Seppo Virtanen, University of Turku, Finland

PAPER ONE

Instrumentation-Driven Model Detection and Actor Partitioning for 
Dataflow Graphs

Ilya Chukhman (Department of Electrical and Computer Engineering, 
Institute for Advanced Computer Studies, University of Maryland, College 
Park, MD, USA), Shuoxin Lin (Department of Electrical and Computer 
Engineering, Institute for Advanced Computer Studies, University of 
Maryland, College Park, MD, USA), William Plishker (Department of 
Electrical and Computer Engineering, Institute for Advanced Computer 
Studies, University of Maryland, College Park, MD, USA), Chung-Ching 
Shen (Department of Electrical and Computer Engineering, Institute for 
Advanced Computer Studies, University of Maryland, College Park, MD, 
USA) and Shuvra S. Bhattacharyya (Department of Electrical and Computer 
Engineering, Institute for Advanced Computer Studies, University of 
Maryland, College Park, MD, USA)

Dataflow modeling offers a myriad of tools to improve optimization and 
analysis of signal processing applications, and is often used by 
designers to help design, implement, and maintain systems on chip for 
signal processing. However, maintaining and upgrading legacy systems 
that were not originally designed using dataflow methods can be 
challenging. Designers often convert legacy code to dataflow graphs by 
hand, a process that can be difficult and time consuming. In this paper, 
the authors developed a method to facilitate this conversion process by 
automatically detecting the dataflow models of the core functions from 
bodies of legacy code. They focus first on detecting static dataflow 
models, such as homogeneous and synchronous dataflow, and then present 
an extension that can also detect dynamic dataflow models. Building on 
the authors’ algorithms for dataflow model detection, they present an 
iterative actor partitioning process that can be used to partition 
complex actors into simpler sub-functions that are more prone to 
analysis techniques.

To obtain a copy of the entire article, click on the link below.
http://www.igi-global.com/article/instrumentation-driven-model-detection-actor/77307

To read a PDF sample of this article, please visit
http://www.igi-global.com/viewtitlesample.aspx?id=77307

 
PAPER TWO

A Simulation-Based Framework for the Exploration of Mapping Solutions on 
Heterogeneous MPSoCs

Antonio Miele (Politecnico di Milano, Milan, Italy), Christian Pilato 
(Politecnico di Milano, Milan, Italy) and Donatella Sciuto (Politecnico 
di Milano, Milan, Italy)

The efficient analysis and exploration of mapping solutions of a 
parallel application on a heterogeneous Multi-Processor Systems-on-Chip 
(MPSoCs) is usually a challenging task in system-level design, in 
particular when the architecture integrates hardware cores that may 
expose reconfigurable features. This paper proposes a system-level 
design framework based on SystemC simulations for fulfilling this task, 
featuring (i) an automated flow for the generation of timing models for 
the hardware cores starting from the application source code, (ii) an 
enhanced simulation environment for SystemC architectures enabling the 
specification and modification of mapping choices only by changing an 
XML descriptor, and (iii) a flexible controller of the simulation 
environment supporting the exploration of various mapping solutions 
featuring a customizable engine. The proposed framework has been 
validated with a case study considering an image processing application 
to show the possibility to automatically exploring alternative solutions 
onto a reconfigurable MPSoC platform.

To obtain a copy of the entire article, click on the link below.
http://www.igi-global.com/article/simulation-based-framework-exploration-mapping/77308

To read a PDF sample of this article, please visit
http://www.igi-global.com/viewtitlesample.aspx?id=77308


 
PAPER THREE

Design Flow for Silicon Chip Implementing Novel Platform Architecture 
for Wireless Communication

Prabhat Avasare (IMEC, Heverlee, Belgium), Jeroen Declerck (IMEC, 
Heverlee, Belgium), Miguel Glassee (IMEC, Heverlee, Belgium), Amir Amin 
(IMEC, Heverlee, Belgium), Erik Umans (IMEC, Heverlee, Belgium), Praveen 
Raghavan (IMEC, Heverlee, Belgium) and Martin Palkovic (IT4Innovations, 
Ostrava, Czech Republic)

In current era of complex chip designs targeting wireless mobile 
terminals, architects and designers need to conform to tight design 
constraints – both in terms of performance (e.g. execution time, silicon 
area, energy consumption) and time-to-market. Further, additional 
flexibility is required in these designs to handle multiple wireless 
standards, sometimes even concurrently. To achieve these challenging 
goals, the authors introduce a platform architecture that uses a 
decentralized control to minimize communication and control overhead 
while keeping timing predictable by using state-of-the-art components 
and a novel interconnect. The authors demonstrate three main 
achievements in running multiple wireless standards on their platform: 
1.053Gbps 4x4 80MHz WLAN 802.11ac receiver data path meeting the SIFS 
timing with a latency of 12.5µs, dual concurrent 173Mbps 2x2 20MHz Cat-4 
3GPP-LTE receiver and platform reconfiguration from WLAN 11n receiver to 
3GPP-LTE one in 52µs. Further the authors describe the design flow used 
to prepare main components of our platform architecture for a tape-out, 
while especially keeping a close eye on energy consumption. We believe 
that our chip design flow is generic and can be used in other custom 
processor chip designs even outside wireless domain.

To obtain a copy of the entire article, click on the link below.
http://www.igi-global.com/article/design-flow-silicon-chip-implementing/77309

To read a PDF sample of this article, please visit
http://www.igi-global.com/viewtitlesample.aspx?id=77309

 
PAPER FOUR

Efficient Implementation of Application-Aware Spinlock Control in MPSoCs

Fabrício A. B. da Silva (Information Technology Division, Brazilian Army 
Technological Center, Rio de Janeiro, Brazil), David F. C. Moura 
(Information Technology Division, Brazilian Army Technological Center, 
Rio de Janeiro, Brazil) and Juraci F. Galdino (Information Technology 
Division, Electrical Engineering Department, Brazilian Army 
Technological Center and Military Institute of Engineering, Rio de 
Janeiro, Brazil)

This survey presents a classification of attacks that Software 
Communications Architecture (SCA) compliant Software Defined Radios 
(SDR) can suffer. This paper also discusses how attack mitigation 
strategies can impact the development of a SCA-compliant software 
infrastructure and identifies several research directions related to SDR 
security. The SCA standard was originally proposed by the Joint Tactical 
Radio System program (JTRS), which is a program for the development of 
military tactical radios sponsored by the US Department of Defense. The 
classification presented in this paper is based on attack results on the 
radio set, which can also be associated with the adversary’s objectives 
when planning an intrusion. The identification of classes of attacks on 
a radio, along with the associated threats and vulnerabilities, is the 
first step in engineering a secure SDR system. It precedes the 
identification of security requirements and the development of security 
mechanisms. Therefore, the identification of classes of attacks is a 
necessary step for the definition of realistic and relevant security 
requirements.

To obtain a copy of the entire article, click on the link below.
http://www.igi-global.com/article/efficient-implementation-application-aware-spinlock/77310

To read a PDF sample of this article, please visit
http://www.igi-global.com/viewtitlesample.aspx?id=77310



*****************************************************
For full copies of the above articles, check for this issue of the 
International Journal of Embedded and Real-Time Communication Systems 
(IJERTCS) in your institution's library.  This journal is also included 
in the IGI Global aggregated "InfoSci-Journals" database:
http://www.igi-global.com/EResources/InfoSciJournals.aspx.
*****************************************************

CALL FOR PAPERS

Mission of IJERTCS:

The mission of the International Journal of Embedded and Real-Time 
Communication Systems (IJERTCS) is to disseminate recent advancements 
and innovations in this interdisciplinary research area for field 
researchers, practitioners, scientists, academicians, students, and IT 
professionals. IJERTCS focuses on overcoming challenges involved in the 
rapid development of embedded communication systems towards feature-rich 
multimedia computers

Coverage of IJERTCS:

The International Journal of Embedded and Real-Time Communication 
Systems (IJERTCS) extensively covers research in the area of embedded 
and real-time communication systems. Within this field, topics to be 
discussed in the journal include (but are not limited to) the following:

Asynchronous and synchronous circuit techniques
Design methods
Embedded networks (built-in networks in embedded communication devices)
Emerging new topics
Fault-tolerant hardware and software technologies
Formal design and verification methods
Hardware and software solutions for protocol processing
Hardware and software solutions for real-time systems
Hardware platforms and technologies
Hardware/software co-design
Modeling and verification methods
On-chip communication in SoC and NoC
OWA (open wireless architecture)
Performance modeling
Platform based design
Real-time computing
Reconfigurable systems
Security issues and technologies
Single-chip SDR (software defined radio) solutions
Software design
Testing techniques


IGI Global is pleased to offer a special Multi-Year Subscription Loyalty 
Program. In this program, customers who subscribe to one or more 
journals for a minimum of two years will qualify for secure subscription 
pricing. IGI Global pledges to cap their annual price increase at 5%, 
which guarantees that the subscription rates for these customers will 
not increase by more than 5% annually.

Interested authors should consult the journal's manuscript submission 
guidelines at www.igi-global.com/ijertcs

All inquiries and submissions should be sent to:
Editor-in-Chief: Seppo Virtanen at seppo.virtanen at utu.fi





More information about the CITAMS mailing list